An effective phase detector for phase-locked loops with wide capture range and fast acquisition time

This paper describes and resolves the false locking issue in phase-locked loops (PLLs) with π-phase detector. In order to verify the proposed approach for acquisition and capture range performances of π-phase detector, the phase-controlled-current-source (PCCS) using the reversing scheme is implemented in TSMC 0.18μm 1P6M CMOS technology. In the simulation results, the locking time of the proposed approach is 6.7X faster than conventional PFD design. Moreover, the measurement results indicate the locking time of testing PLL is less than 2μs.