Q8WARE: Synthesis Tool for Network-on-Chip Applications

Author

Habib, Sami J. ; Mohammad, Mohammad Gh

Author_Institution

Kuwait Univ.

fYear

2006

fDate

Nov. 2006

Firstpage

1

Lastpage

5

Abstract

Setting up of an assembly line for the manufacturing of application-specific integrated circuits (ASICs) is very expensive, which may cost in the range of several hundred million dollars, and may take several manpower years. In this paper, we present Q8WARE tool, which is a small-scale version of an ASIC assembly line through the usage of Altera education FPGA board (UP2) and Verilog Q8WARE is adaptable for the manufacturing heterogeneous ASICs through the reusability of hardware modules between heterogeneous ICs. We have explored the implementation of a token ring to be used as a network-on-chip (NoC) with various protocol reconfigurations

Keywords

application specific integrated circuits; design for manufacture; field programmable gate arrays; hardware description languages; network-on-chip; reconfigurable architectures; ASIC assembly line; Altera education FPGA board; Verilog Q8WARE; application-specific integrated circuits; hardware modules; network-on-chip applications; protocol reconfigurations; synthesis tool; Application specific integrated circuits; Assembly; Costs; Field programmable gate arrays; Hardware design languages; Integrated circuit manufacture; Integrated circuit synthesis; Network synthesis; Network-on-a-chip; Pulp manufacturing;

fLanguage

English

Publisher

ieee

Conference_Titel

Innovations in Information Technology, 2006

Conference_Location

Dubai

Print_ISBN

1-4244-0674-9

Electronic_ISBN

1-4244-0674-9

Type

conf

DOI

10.1109/INNOVATIONS.2006.301925

Filename

4085440