Comparison of isothermal wafer-level EM and package-level EM for via test structure in dual damascene low k/Copper process

In this study, an isothermal wafer-level electromigration (EM) test method has been applied in via test-structure. The dual damascene low k/Copper process was evaluated by such a highly accelerated test way. A test structure with 0.28um via landed on metal line-end was used and stressed with downstream electronic direction. By using five kinds of liner processes, the results of wafer-level reliability (WLR) and packager-level reliability (PLR) are compared. The lifetime and shape factor projection from package-level to wafer-level is significant under these processes. The current exponent and activation energy of both methods were also investigated. The activation energy will be optimistic while WLR test temperature is below 400°C. While the test condition is below 400°C, the activation energy value of WLR will be more close to PLR. Finally, the failure mode of WLR and PLR will also be compared and discussed.