TICER: Realizable reduction of extracted RC circuits

Time Constant Equilibration Reduction (TICER) is a novel RC reduction method tailored for extract/reduce CAD tools. Geometry-minded extraction tools fracture nets into parasitics based on local changes in geometry. The resulting RC circuits can have a huge dynamic range of time-constants; by eliminating the extreme time-constants, TICER produces smaller, less-stiff RC networks. It produces realizable RC circuits; can retain original network topology; scales well to large networks (/spl sim/10/sup 7/ nodes); preserves dc and ac behavior; handles resistor loops and floating capacitors; has controllable accuracy; operates in linear time on most nets.