Title :
Analytical macromodeling for high-level power estimation
Author :
Bernacchia, G. ; Papaefthymiou, M.C.
Author_Institution :
Dipt. di Elettrotecnica, Elettronica ed Inf., Trieste Univ., Italy
Abstract :
This paper presents a new macromodeling technique for high-level power estimation. Our technique is based on a parameterizable analytical model that relies exclusively on statistical information of the circuit´s primary inputs. During estimation, the statistics of the required metrics are extracted from the input stream, and a power estimate is obtained by evaluating a model function that has been characterized in advance. Our model yields power estimates within seconds, because it does not rely on the statistics of the circuit´s primary outputs and, consequently, does not perform any simulation during estimation. Moreover, it achieves better accuracy than previous macromodeling approaches by taking into account both spatial and temporal correlations in the input stream. In experiments with the ISCAS-85 combinational circuits, the average absolute relative error of our power macromodeling technique was at most 1.8%. The worst-case error was at most 12.8%. For a ripple-carry adder family, in comparison with power estimates that were obtained using Spice, the average absolute and worst-case errors of our model´s estimates were at most 5.1% and 19.8%, respectively. In addition to power dissipation, our macromodeling technique can be used to estimate the statistics of a circuit´s primary outputs with very low average errors. It is thus suitable for power estimation in core-based systems with pre-characterized blocks. Once the metrics of the primary inputs are known, the power dissipation of the entire system can be estimated by simply propagating this information through the blocks using their corresponding model functions.
Keywords :
SPICE; circuit simulation; combinational circuits; logic testing; ISCAS-85 combinational circuits; Spice; analytical macromodeling; average absolute relative error; high-level power estimation; parameterizable analytical model; statistical information; temporal correlations; worst-case error; Adders; Analytical models; Circuit simulation; Combinational circuits; Data mining; Error analysis; Power dissipation; Power system modeling; Statistics; Yield estimation;
Conference_Titel :
Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-5832-5
DOI :
10.1109/ICCAD.1999.810662