Title :
Validation and test generation for oscillatory noise in VLSI interconnects
Author :
Sinha, A. ; Gupta, S.K. ; Breuer, M.A.
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
Inductance of on-chip interconnects gives rise to signal overshoots and undershoots that can cause logic errors. By considering technology trends, we show that in 0.13 /spl mu/m technology such noise in local interconnects embedded in combinational logic can exceed the threshold voltage. We show the impact of such noise on different kinds of circuits. The magnitude of this noise can increase due to process variations. We present an algorithm for generating vectors for validation and manufacturing test to detect logic-value errors caused by inductance induced oscillation. To facilitate the vector generation method, we have derived analytical expressions, as functions of rise and fall times for (i) the magnitude of overshoots and undershoots, and (ii) the settling time, i.e., the time required for the circuit response to settle to a bound close to the final value.
Keywords :
VLSI; combinational circuits; integrated circuit interconnections; integrated circuit testing; logic testing; VLSI interconnects; circuit response; combinational logic; logic errors; logic-value errors; manufacturing test; on-chip interconnects; oscillatory noise; signal overshoots; test generation; validation; vector generation method; Circuit noise; Circuit testing; Crosstalk; Inductance; Integrated circuit interconnections; Integrated circuit noise; Logic; Noise generators; Switching circuits; Very large scale integration;
Conference_Titel :
Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-5832-5
DOI :
10.1109/ICCAD.1999.810664
