Title :
An on-chip waveform capturing technique pursuing minimum cost of integration
Author :
Araga, Yuuki ; Hashida, Takushi ; Nagata, Makoto
Author_Institution :
Dept. of Comput. Sci. & Syst. Eng., Kobe Univ., Kobe, Japan
fDate :
May 30 2010-June 2 2010
Abstract :
An on-chip waveform capturing technique demonstrates 8.5 ENOB and 62.7 dB SFDR at 200 Ms/s for analog signals with 25-MHz bandwidth and 2.5 V rail-to-rail offset DC level, suitable for testing and self diagnosis of a mixed-signal chip. The area of 0.004mm2 in a 90 nm CMOS chip is only required for the integration of probing front end circuitry, with the help of an efficient discretization algorithm on a digital data processing chain involving on-chip logic paths, an off-chip 8 bit micro controller, and PC. Waveform acquisition at the system throughput of 1.9 transaction/point is achieved, by minimizing the number of slow-speed transactions between external measurement equipments and PC.
Keywords :
CMOS integrated circuits; logic circuits; low-power electronics; microprocessor chips; mixed analogue-digital integrated circuits; CMOS chip; analog signals; bandwidth 25 MHz; digital data processing; discretization algorithm; mixed-signal chip; on-chip logic paths; on-chip waveform capturing technique; rail-to-rail offset DC level; size 90 nm; voltage 2.5 V; waveform acquisition; word length 8 bit; Automatic testing; Bandwidth; CMOS digital integrated circuits; CMOS logic circuits; CMOS process; Circuit testing; Control systems; Costs; Data processing; System-on-a-chip;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537814
