Title :
A cyclic vernier time-to-digital converter synthesized from a 65nm CMOS standard library
Author :
Park, Youngmin ; Wentzloff, David D.
Author_Institution :
Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA
fDate :
May 30 2010-June 2 2010
Abstract :
This paper presents a synthesizable cyclic Vernier time-to-digital converter (TDC) with digitally controlled oscillators (DCOs). All functional blocks in the TDC are implemented with digital standard cells and placed-and-routed (PAR) by automatic design tools; thus, the TDC is portable and scalable to other process technologies. The effect of PAR mismatch is characterized in the post-layout simulation and utilized to achieve 1ps TDC resolution. The TDC was designed in a 65nm CMOS process, and occupies 0.001mm2.
Keywords :
CMOS integrated circuits; CMOS standard library; automatic design tool; cyclic vernier time-to-digital converter; digital standard cells; digitally controlled oscillator; placed-and-routed; post-layout simulation; process technology; size 65 nm; synthesizable cyclic Vernier time-to-digital converter; Analog circuits; Automatic control; Calibration; Circuit synthesis; Counting circuits; Digital circuits; Digital control; Frequency; Oscillators; Software libraries;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537815
