DocumentCode
3387568
Title
On low-capture-power test generation for scan testing
Author
Wen, Xiaoqing ; Yamashita, Yoshiyuki ; Kajihara, Seiji ; Wang, Laung-Terng ; Saluja, Kewal K. ; Kinoshita, Kozo
Author_Institution
Dept. of CSE, Kyushu Inst. of Technol., Iizuka, Japan
fYear
2005
fDate
1-5 May 2005
Firstpage
265
Lastpage
270
Abstract
Research on low-power scan testing has been focused on the shift mode, with little or no consideration given to the capture mode power. However, high switching activity when capturing a test response can cause excessive IR drop, resulting in significant yield loss. This paper addresses this problem with a novel low-capture-power X-filling method by assigning 0´s and 1´s to unspecified (X) bits in a test cube to reduce the switching activity in capture mode. This method can be easily incorporated into any test generation flow, where test cubes are obtained during ATPG or by X-bit identification. Experimental results show the effectiveness of this method in reducing capture power dissipation without any impact on area, timing, and fault coverage.
Keywords
automatic test pattern generation; boundary scan testing; built-in self test; flip-flops; integrated circuit testing; low-power electronics; ATPG; X-bit identification; X-filling method; capture mode power; low-capture-power test generation; scan testing; switching activity; test cubes; test generation flow; test response; yield loss; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Flip-flops; Integrated circuit testing; Logic testing; Power dissipation; Sequential analysis; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 2005. Proceedings. 23rd IEEE
ISSN
1093-0167
Print_ISBN
0-7695-2314-5
Type
conf
DOI
10.1109/VTS.2005.60
Filename
1443434
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