Design of adaptive nanometer digital systems for effective control of soft error tolerance

Nanometer circuits are highly susceptible to soft errors generated by alpha-particle or atmospheric neutron strikes to circuit nodes. The reasons for the high susceptibility are the reduced node capacitances and noise margins caused by feature size and supply voltage scaling. Static soft error optimization (such as concurrent error detection or gate resizing) can be very expensive in terms of power consumption if the circuit is not always exposed to high flux of particles. This paper proposes a scheme for dynamic control of soft error tolerance in digital circuits that has negligible power and delay overhead when the circuit is in its normal mode of operation. The key objective is to design circuits that can adapt to different radiation conditions with minimal power overhead. The soft error rate of the circuit is monitored by simple on-chip circuitry, and circuit soft error tolerance is controlled by using dynamic supply voltage and threshold voltage modulation together with variable capacitance banks.