8C: IP Session - Test Resource Partitioning in Action [Breaker page]

The arrival of nanometer design brings in its own technical and economical challenges. Testing these chips via a traditional ATE alone may be prohibitively expensive or may simply be impossible due to physical constraints. Test Resource Partitioning is a way to handle these problems by partitioning the test resources appropriately along the signal path from ATE to DUT. A test solution can have its components residing on ATE, DFT, Probe card, interposer or Loadboard. The partitioning of the test resources depends on the problem at hand and requires collaboration of test components in the solution and not to mention the necessary EDA tool support. This session with present some of the Innovative TRP solutions/components that have been developed in the industry to solve the test problem.