DocumentCode
3387740
Title
Improving area efficiency of FIR filters implemented using distributed arithmetic
Author
Sinha, Amit ; Mehendale, Mahesh
Author_Institution
Dept. of Electr. Eng., Indian Inst. of Technol., New Delhi, India
fYear
1998
fDate
4-7 Jan 1998
Firstpage
104
Lastpage
109
Abstract
In this paper we present techniques for improving area efficiency of FIR filters implemented using the distributed arithmetic (DA) approach. These techniques exploit the flexibility in partitioning the filter coefficients for a two lookup-table (LUT) based DA implementation. The first technique is targeted at a ROM based implementation of LUTs and aims at minimizing number of columns/outputs of the ROMs. The second technique is targeted at a hardwired implementation of LUTs. We have developed an estimation technique for relative area comparisons of hardwired LUTs having the same number of inputs and outputs. We present a heuristic approach, based on this estimation technique, to optimally partition coefficients so as to achieve area-efficient hardwired implementation of LUTs. We present results to show these techniques can result in 10% to 15% area reduction for ROM based implementations and 20% to 25% area reduction for hardwired implementations
Keywords
FIR filters; VLSI; digital arithmetic; digital filters; table lookup; FIR filters; ROM based implementation; area efficiency; distributed arithmetic; filter coefficients; hardwired implementation; heuristic approach; lookup-table based implementation; relative area comparisons; Arithmetic; Digital signal processing; Dynamic range; Finite impulse response filter; Home computing; Instruments; Nonlinear filters; Read only memory; Table lookup; Upper bound;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on
Conference_Location
Chennai
ISSN
1063-9667
Print_ISBN
0-8186-8224-8
Type
conf
DOI
10.1109/ICVD.1998.646586
Filename
646586
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