Abstract :
Summary form only given, as follows. Identification of systematic marginalities affecting unstructured logic requires a combination of DFT solutions, diagnosis techniques, and a lot of data from multiple sources. This panel wants to discuss the role and the challenges of DFT and test manufacturing in the yield learning process - What is needed? Which are the challenges? Which are the potential/existing bottlenecks? The panelists are from the EDA world, are developing and supplying integrated data management solutions, and are engaged in bringing VDSM technologies to maturity. Panelists: E. Chang, KLA Tencor; H. Fatemi, Yield Dynamics; C. Guardiani, PDF Solutions; Greg Yeric, HPL; and Rohit Kapur, Synopsys.
