Title :
Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency
Author :
Alioto, Massimo ; Consoli, Elio ; Palumbo, Gaetano
Author_Institution :
Dept. of Inf. Eng., Univ. of Siena, Siena, Italy
fDate :
May 30 2010-June 2 2010
Abstract :
In this paper, an optimization strategy is proposed for Dual Edge-Triggered (DET) clock distribution in clock domains, based on the proper choice of the clock slope. The suggested approach takes full advantage of the intrinsic features of DET Flip-Flops to achieve up to 50% energy-savings compared to traditional DET design approaches. The speed penalty, in terms of both FFs delay and local skew/jitter, is proven to be negligible through extensive simulations in a 65-nm CMOS technology.
Keywords :
CMOS integrated circuits; clocks; flip-flops; jitter; CMOS technology; DET design; FF delay; clock domains; clock slope; dual edge-triggered clock distribution; dual-edge-triggered flip-flops; energy efficiency; jitter; local skew; CMOS technology; Clocks; Delay; Energy efficiency; Flip-flops; Inverters; Jitter; Modeling; Parasitic capacitance; Power engineering and energy;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537828
