Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency

In this paper, an optimization strategy is proposed for Dual Edge-Triggered (DET) clock distribution in clock domains, based on the proper choice of the clock slope. The suggested approach takes full advantage of the intrinsic features of DET Flip-Flops to achieve up to 50% energy-savings compared to traditional DET design approaches. The speed penalty, in terms of both FFs delay and local skew/jitter, is proven to be negligible through extensive simulations in a 65-nm CMOS technology.