A 16Kb 10T-SRAM with 4x read-power reduction

Author

Hui, Kong Zhi ; Tuan, Do Anh

Author_Institution

Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore

fYear

2010

fDate

May 30 2010-June 2 2010

Firstpage

3485

Lastpage

3488

Abstract

This work aims to reduce the read power consumption as well as to enhance the stability of the SRAM cell during the read operation. A new 10-transisor cell is proposed with a new read scheme to minimize the power consumption within the memory core. It has separate read and write ports, thus cell read stability is significantly improved. A 16Kb SRAM macro operating at 1V supply voltage is demonstrated in 65 nm CMOS process. Its read power consumption is reduced to 24% of the conventional design. The new cell also has lower leakage current due to its special bit-line pre-charge scheme. As a result, it is suitable for low-power mobile applications where power supply is restricted by the battery.

Keywords

CMOS memory circuits; SRAM chips; circuit stability; low-power electronics; power consumption; readout electronics; transistor circuits; CMOS process; SRAM cell; bit rate 16 kbit/s; bit-line precharge scheme; cell read stability; leakage current; low-power mobile application; memory core; power supply; read operation; read port; read power consumption; read-power reduction; size 65 nm; transisor cell; voltage 1 V; write port; CMOS technology; Decoding; Driver circuits; Energy consumption; Integrated circuit technology; Leakage current; Power amplifiers; Random access memory; Stability; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Conference_Location

Paris

Print_ISBN

978-1-4244-5308-5

Electronic_ISBN

978-1-4244-5309-2

Type

conf

DOI

10.1109/ISCAS.2010.5537830

Filename

5537830