Dynamic logic families for complementary gallium arsenide (CGaAs) fabrication processes

Author

Fouls, D.J. ; Shehata, Khaled Ali ; Michael, Sherif

Author_Institution

Dept. of Electr. & Comput. Eng., Naval Postgraduate Sch., Monterey, CA, USA

Volume

2

fYear

1997

fDate

3-6 Aug. 1997

Firstpage

1107

Abstract

Different Complementary Gallium Arsenide (CGaAs) dynamic logic circuits have been designed, simulated and implemented. The circuits include Domino, N-P Domino, and Two-Phase Dynamic FET Logic (TPDL). These circuits are investigated and compared against complementary static logic for speed, power consumption and layout area. TPDL circuits are the fastest (function properly up to 2.38 GHz) and have the lowest power consumption ever reported in this technology (0.01 μW/MHz/gate). Moreover, TPDL circuits are self latching and well suited for pipelined architectures.

Keywords

field effect logic circuits; gallium arsenide; logic design; 2.38 GHz; GaAs; TPDL circuits; complementary GaAs fabrication processes; domino logic; dynamic logic families; layout area; pipelined architectures; power consumption; self latching type; two-phase dynamic FET logic; CMOS logic circuits; CMOS technology; Clocks; Energy consumption; FETs; Fabrication; Gallium arsenide; Logic circuits; Logic design; Pulse inverters;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on

Print_ISBN

0-7803-3694-1

Type

conf

DOI

10.1109/MWSCAS.1997.662271

Filename

662271