Title :
Experimental evaluation of bridge patterns for a high performance microprocessor
Author :
Chakravarty, Sreejit ; Chang, YiShing ; Hoang, Hiep ; Jayaraman, Sridhar ; Picano, Silvio ; Prunty, Cheryl ; Savage, Eric W. ; Sheikh, Rehan ; Tran, Eric N. ; Wee, Khen
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
Silicon evaluation of scan patterns, targeting realistic bridges, for a high performance microprocessor is presented. The practicality of generating realistic bridge patterns is demonstrated. Silicon data, with and without functional fails, and in the presence of n-detect tests are presented. Data points to the value of and efficiency of bridge patterns. Data also shows the advantage of using supplemental bridge patterns when compared with supplemental stuck-at patterns.
Keywords :
integrated circuit testing; logic testing; microprocessor chips; bridge patterns; functional fails; high performance microprocessor; n-detect tests; scan patterns; silicon evaluation; stuck-at patterns; Automatic test pattern generation; Bridge circuits; Circuit faults; Circuit testing; Educational institutions; Fault detection; Logic testing; Microprocessors; Silicon; Test pattern generators;
Conference_Titel :
VLSI Test Symposium, 2005. Proceedings. 23rd IEEE
Print_ISBN :
0-7695-2314-5
DOI :
10.1109/VTS.2005.44
