A BIST scheme for testing analog-to-digital converters with digital response analyses

This paper presents a built-in self-test (BIST) scheme for testing ADC s static parameters that include offset error, gain error, integral non-linearity (INL) and differential non-linearity (DNL). The main components in the scheme contain control circuit, differential integrator and test response analyzer (TRA). A system clock pulse is used to trig a counter and inputted to control circuit that regulates the frequency, duty cycle and amplitude of the system clock pulse to output a regulated clock signal (RLK). The RLK is integrated by the integrator to become a called step-ramp stimulus. The correct synchronization between the step-ramp stimulus and the counter output codes is achieved. Then the digital TRA can be designed by analyzing the ADC´s output codes and the references of the counter´s output codes. With the integration of gradually increasing duty cycles of the RLK to compensate the nonlinear leakage currents depending on the increasing voltages of the integrator, the high accurate step-ramp stimulus is generated. Simulation results show that the accuracies of all step-ramp pieces of the stimulus are within 0.5% LSB.