DocumentCode :
3388041
Title :
Partitioning and synthesis for hybrid architecture simulators
Author :
Ruan, Zhuo ; Penry, David A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
fYear :
2010
fDate :
May 30 2010-June 2 2010
Firstpage :
1859
Lastpage :
1862
Abstract :
Pure software simulators are too slow to simulate modern complex computer architectures and systems. Hybrid software/hardware simulators have been proposed to accelerate architecture simulation. However, the design of the hardware portions and hardware/software interface of the simulator is time-consuming, making it difficult to modify and improve these simulators. We here describe the Simulation Partitioning Research Infrastructure (SPRI), an infrastructure which partitions the software architectural model under user guidance and automatically synthesizes hybrid simulators. We also present a case study using SPRI to investigate the performance limitations and bottlenecks of the generated hybrid simulators.
Keywords :
hardware-software codesign; software architecture; architecture; hardware-software interface; hybrid software-hardware architecture simulators; simulation partitioning research infrastructure; software architectural model; Acceleration; Computational modeling; Computer architecture; Computer simulation; Hardware; Hybrid power systems; Libraries; Process design; Signal synthesis; Synthesizers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
Type :
conf
DOI :
10.1109/ISCAS.2010.5537839
Filename :
5537839
Link To Document :
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