Frequency-overscaling DSP circuit design with reduced-precision redundancy and subword detection processing

Reduced-precision redundancy (RPR) technique has recently developed for voltage-overscaling (VOS) low-power DSP circuit design and soft error tolerance. In this paper, we combine the RPR technique with a frequency-overscaling (FOS) technique and propose a subword-detection processing technique to increase the speed of a DSP circuit. The proposed techniques can improve the clock speed with acceptable noise degradation by employing a reduced-precision replica of main DSP module. We design and implement an FOS FFT processor with the RPR and SDP techniques. The simulation results show that the proposed techniques can improve the SNR performance by 34.5 dB when the operating frequency is overscaled to 1.21 times of the maximal achievable frequency.