DocumentCode :
3388054
Title :
Testing the interconnect networks and I/O resources of field programmable analog arrays
Author :
Pereira, Gustavo ; Lubaszewski, Marcelo ; Andrade, Antonio, Jr. ; Balen, Tiago R. ; Azais, Florence ; Renovell, Michel
Author_Institution :
Inst. de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
fYear :
2005
fDate :
1-5 May 2005
Firstpage :
389
Lastpage :
394
Abstract :
The test of field programmable analog arrays (FPAA) may be performed based on partitioning these devices in three main parts: I/O cells, interconnection networks and configurable analog blocks. In this work, a scheme for testing the I/O cells and the local and global interconnection networks of FPAAs is proposed, using an adjacency graph model to represent the programmable interconnection and I/O resources, and then devising a set of test configurations (TC) by solving graph coloring problems. The goal is to achieve a near minimum number of TCs ensuring all stuck-open and stuck-on faults in switches, as well as opens and shorts in wires, are covered. Large parametric faults in interconnects are implicitly covered in these TCs by judiciously choosing test stimuli and, in I/O buffers, by means of an oscillation-based test strategy.
Keywords :
analogue integrated circuits; fault diagnosis; field programmable analogue arrays; graph colouring; integrated circuit interconnections; integrated circuit testing; I/O resources; adjacency graph model; configurable analog blocks; field programmable analog arrays; graph coloring problems; interconnect networks; oscillation-based test; programmable interconnection; stuck-on faults; stuck-open fault; test configurations; Analog circuits; Circuit faults; Circuit testing; Field programmable analog arrays; Integrated circuit interconnections; Multiprocessor interconnection networks; Performance evaluation; Phased arrays; Switches; Wires; FPAA testing; Mixed-signal test; interconnect testing; oscillation-based test;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2005. Proceedings. 23rd IEEE
ISSN :
1093-0167
Print_ISBN :
0-7695-2314-5
Type :
conf
DOI :
10.1109/VTS.2005.85
Filename :
1443454
Link To Document :
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