Benchmark Circuit Complexity Validation using Binary Decision Diagram Characteristics

Author

Mills, Bruce ; Prasad, P.W.C. ; Prasad, V.C.

Author_Institution

Coll. of Inf. Technol., United Arab Emirates Univ., Al Ain

fYear

2006

fDate

Nov. 2006

Firstpage

1

Lastpage

5

Abstract

It has been shown that when binary decision diagrams (HDDs) are formed from uniformly distributed random Boolean functions (BFs), the average number of nodes in the BDDs is in a simple relation to the number of variables and terms in the BFs. In the present work, the node counts for BBDs formed from ISCAS benchmark circuits are examined and compared to the results for random BFs. The model for random BFs is shown to have strong descriptive power for the benchmark data. Therefore, the model is promoted as a method of predicting, for a given BF, circuit complexity measures such as the area of a VLSI implementation

Keywords

Boolean functions; binary decision diagrams; circuit complexity; electronic engineering computing; ISCAS benchmark circuit; VLSI implementation; benchmark circuit complexity; binary decision diagram; distributed random Boolean function; Benchmark testing; Binary decision diagrams; Boolean functions; Circuit testing; Complexity theory; Data structures; Design automation; Educational institutions; Mathematical model; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Innovations in Information Technology, 2006

Conference_Location

Dubai

Print_ISBN

1-4244-0674-9

Electronic_ISBN

1-4244-0674-9

Type

conf

DOI

10.1109/INNOVATIONS.2006.301966

Filename

4085481