DocumentCode :
3388121
Title :
An economic selecting model for DFT strategies
Author :
Lin, Yu-Ting ; Ambler, Tony
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Texas, Austin, TX, USA
fYear :
2005
fDate :
1-5 May 2005
Firstpage :
412
Lastpage :
417
Abstract :
Exploiting the knowledge-based technology and multi-objective analysis, this paper presents a selecting model and its prototype implementation for design for testability (DFT) strategies. Cores to the knowledge-based selecting are decision tree-based knowledge representation models. Keys to the decision tree model are human-like decision procedures and time elimination of defining cost related equations. Test runs over a design-and-test compatible environment demonstrate both feasibility and potential effectiveness of the decision tree selecting model to support both the current and future needs of VLSI testing.
Keywords :
VLSI; decision trees; design for testability; integrated circuit testing; knowledge based systems; knowledge representation; DFT strategies; VLSI testing; cost related equations; decision tree; design for testability; design-and-test compatible environment; economic selecting model; human-like decision procedures; knowledge representation models; knowledge-based selecting; knowledge-based technology; multiobjective analysis; Costs; Data mining; Decision making; Decision trees; Design for testability; Environmental economics; Graphical user interfaces; Knowledge representation; Logic testing; Sensitivity analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2005. Proceedings. 23rd IEEE
ISSN :
1093-0167
Print_ISBN :
0-7695-2314-5
Type :
conf
DOI :
10.1109/VTS.2005.29
Filename :
1443458
Link To Document :
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