DocumentCode :
3388176
Title :
Memory binding for performance optimization of control-flow intensive behaviors
Author :
Khouri, K.S. ; Lakshminarayana, G. ; Jha, N.K.
Author_Institution :
Dept. of Electr. Eng., Princeton Univ., NJ, USA
fYear :
1999
fDate :
7-11 Nov. 1999
Firstpage :
482
Lastpage :
488
Abstract :
The paper presents a memory binding algorithm for behaviors that are characterized by the presence of conditionals and deeply-nested loops that access memory extensively through arrays. Unlike previous works, this algorithm examines the effects of branch probabilities and allocation constraints. First, we demonstrate through examples, the importance of incorporating branch probabilities and allocation constraint information when searching for a performance-efficient memory binding. We also show the interdependence of these two factors and how varying one without considering the other may greatly affect the performance of the behavior. Second, we introduce a memory binding algorithm that has the ability to examine numerous bindings by employing an efficient performance estimation procedure. The estimation procedure exploits locality of execution, which is an inherent characteristic of target behaviors. This enables the performance estimation technique to look at the global impact of the different bindings, given the allocation constraints. We tested our algorithm using a number of benchmarks from the parallel computing domain. A series of experiments demonstrates the algorithm´s ability to produce bindings that optimize performance, meet memory allocation constraints, and adapt to different resource constraints and branch probabilities. Results show that the algorithm requires 37% fewer memories with a performance loss of only 0.3% when compared to a parallel memory architecture. When compared to the best of a series of random memory bindings, the algorithm improves schedule performance by 21%.
Keywords :
memory architecture; parallel algorithms; probability; resource allocation; storage management; allocation constraints; branch probabilities; conditionals; control-flow intensive behaviors; deeply-nested loops; global impact; locality of execution; memory allocation constraints; memory binding algorithm; parallel computing; parallel memory architecture; performance estimation procedure; performance estimation technique; performance optimization; performance-efficient memory binding; random memory bindings; resource constraints; schedule performance; Benchmark testing; Constraint optimization; Memory architecture; Memory management; National electric code; Parallel processing; Performance analysis; Performance loss; Resource management; Scheduling algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
ISSN :
1092-3152
Print_ISBN :
0-7803-5832-5
Type :
conf
DOI :
10.1109/ICCAD.1999.810698
Filename :
810698
Link To Document :
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