FinFET scaling rule based On variability considerations

FinFETs electrostatics depends largely on the fin width (W_FIN). Herein we demonstrate that an optimal W_FIN exists at which the variability is minimized. We present in this work that at higher W_FIN, degraded electrostatics causes both gate edge roughness (GER) and line edge roughness (LER) based variability to degrade. On the other hand, at lower W_FIN, LER induced quantum confinement (QC) strongly degrades variability [1]. Thus an optimized W_FIN/L_G ratio for different technology nodes based on variability is obtained, which is nearly 0.33. The obtained ratio is in the range of electrostatics thumb-rule for W_FIN/L_G (=0.25-0.5) [2]. Also, at constant LER/GER 3σ (=2 nm), V_T variability increases strongly with scaling. To enable constant V_T variability, the LER/GER 3σ (in nm) patterning variability requirement is also presented.