Title :
Symbolic functional and timing verification of transistor-level circuits
Author :
McDonald, C.B. ; Bryant, R.E.
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaustively verify a medium-sized modern logic block. Static analysis can handle much larger circuits but is not robust with respect to variations from standard circuit structures. Our approach applies symbolic simulation to analyze a circuit over all input combinations without these limitations. We present a prototype simulator (SirSim) and experimental results. We also discuss using SirSim to verify an industrial design which previously required a special-purpose verification methodology.
Keywords :
CMOS logic circuits; formal verification; logic CAD; logic simulation; timing; transistor circuits; SirSim; custom CMOS circuits; simulation; static analysis; symbolic simulation; symbolic verification; timing verification; transistor-level circuits; Analytical models; CMOS logic circuits; Circuit simulation; Computational modeling; Delay; Discrete event simulation; Latches; Pattern analysis; Robustness; Timing;
Conference_Titel :
Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-5832-5
DOI :
10.1109/ICCAD.1999.810706
