Adaptive and dynamic reconfigurable multiprocessor system to improve software productivity

Nowadays, multiprocessor system-on-chips (MPSoCs) are employed in a heterogeneous fashion, being composed of application-specific integrated circuits (ASICs) and processors that implement different instruction set architectures (ISAs). Because of that, there are two main issues. First, the lack of adaptability, since ASICs are designed for a specific purpose and cannot be changed after deployment; second, the necessity to code for different ISAs, which involves different tool chains which increases design time. In this scenario, the authors propose custom-reconfigurable arrays for multiprocessor systems (CReAMS), which is composed of multiple processors that implement a unique ISA, each of them coupled to an adaptive reconfigurable system, so it is possible to simultaneously exploit instruction-level and thread-level parallelism. Differently from most reconfigurable architectures there is no need to change the binary/source code, nor software development process or environment, which guarantees software compatibility; and in contrast to current MPSoCs used in embedded systems, it is capable of adapting to accelerate applications that were not considered at design time. Besides the obvious advantages in software productivity, CReAMS outperforms a multiprocessor with single-issue processors by 19% and reduces 70% of the energy consumption. In addition, CReAMS outperforms a four-issue out-of-order superscalar processor by 18% in a power budget scenario.