DocumentCode :
3388480
Title :
A ´do-it-yourself´ methodology for CMOS transistor mismatch characterization
Author :
Serrano-Gotarredona, Teresa ; Linares-Barranco, Bernabé
Author_Institution :
Dept. of Analog Design, Nat. Microelectron. Center, Seville, Spain
Volume :
2
fYear :
1997
fDate :
3-6 Aug. 1997
Firstpage :
1120
Abstract :
This paper presents a ´do-it-yourself´ methodology for characterizing the random component of transistor mismatch in CMOS technologies. The methodology is based on the design of a special purpose chip which allows automatic characterization of arrays of NMOS and PMOS transistors of different sizes. Up to 30 different transistor sizes were implemented in the same chip, sweeping transistors width W and length L. The standard deviation of the mismatch of these parameters is computed (σ(Δβ/β), σ(Δvγ0), σ(Δγ)) for each transistor type and size, as well as the statistical correlation factors between them. These standard deviations and correlations are fitted to two dimensional surfaces σ(W, L) so that their values can be predicted as a function of transistor sizes. These functions are used in an electrical circuit simulator (Hspice) to predict transistor mismatch. Measured and simulated data are in good agreement.
Keywords :
CMOS integrated circuits; circuit analysis computing; integrated circuit layout; integrated circuit modelling; interpolation; statistical analysis; CMOS transistor mismatch; Hspice; electrical circuit simulator; interpolation surfaces; mismatch characterization methodology; standard deviations; statistical correlation factors; transistor sizes; CMOS technology; Circuit simulation; Doping; Implants; MOS devices; MOSFETs; Microelectronics; Performance evaluation; Predictive models; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on
Print_ISBN :
0-7803-3694-1
Type :
conf
DOI :
10.1109/MWSCAS.1997.662274
Filename :
662274
Link To Document :
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