32 bit GaAs HFET IEEE floating point multiplier

Author

Tate, L.R. ; Niescier, R.J. ; Hu, A.C. ; Scorzelli, J. ; Leung, W.-B. ; Tzinis, C.H. ; Robertson, P.J. ; Baca, A.

Author_Institution

AT&T Bell Labs., Allentown, PA, USA

fYear

1997

fDate

4-7 Oct. 1997

Firstpage

85

Lastpage

88

Abstract

Presents a floating point multiplier IC fabricated in 1- mu m self-aligned gate GaAs heterostructure technology. By application of full custom layout techniques and a time-optimum architecture, the authors achieved 9.25-ns total latency IEEE single basic format multiplies with 7-W power consumption at room temperature. At 6500 gates, this implies a speed times power product of 140 fJ/gate.<>

Keywords

III-V semiconductors; application specific integrated circuits; field effect integrated circuits; gallium arsenide; integrated logic circuits; multiplying circuits; 32 bits; 7 W; 9.25 ns; IEEE single basic format multiplies; floating point multiplier IC; full custom layout techniques; self-aligned gate GaAs heterostructure technology; speed times power product; time-optimum architecture; total latency; Etching; Gallium arsenide; HEMTs; Knee; Logic circuits; MODFETs; Packaging; Power supplies; Schottky diodes; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1992. Technical Digest 1992., 14th Annual IEEE

Conference_Location

Miami Beach, FL, USA

Print_ISBN

0-7803-0773-9

Type

conf

DOI

10.1109/GAAS.1992.247217

Filename

247217