DocumentCode :
3388653
Title :
A technique to improve capture range of a PLL in PRML read channel
Author :
Srinivasan, Chellam
Author_Institution :
Mixed Signal Design Centre, Texas Instrum., Bangalore
fYear :
1998
fDate :
4-7 Jan 1998
Firstpage :
145
Lastpage :
149
Abstract :
A new technique to improve the capture range of a Phase Locked Loop (PLL) in the context of partial response signalling is presented. A known preamble is transmitted at the beginning to aid phase and frequency locking. Previous timing recovery techniques have a false locking problem for large initial frequency errors. The new technique eliminates this problem by using information available in the sampled preamble sequence. The improvement obtained is demonstrated using computer simulations
Keywords :
hard discs; maximum likelihood detection; partial response channels; phase locked loops; PLL; PRML read channel; capture range; computer simulations; false locking problem; initial frequency errors; partial response signalling; sampled preamble sequence; Computer errors; Error correction; Frequency; Instruments; Intersymbol interference; Partial response channels; Phase locked loops; Sampling methods; Signal design; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on
Conference_Location :
Chennai
ISSN :
1063-9667
Print_ISBN :
0-8186-8224-8
Type :
conf
DOI :
10.1109/ICVD.1998.646593
Filename :
646593
Link To Document :
بازگشت