Title :
A method of test generation for weakly testable data paths using test knowledge extracted from RTL description
Author :
Ohtake, Satoshi ; Inoue, Michiko ; Fujiwara, Hideo
Author_Institution :
Graduate Sch. of Inf. Sci, Nara Inst. of Sci. & Technol., Japan
Abstract :
Weak testability is a testability measure for register-transfer level (RTL) data paths. If a data path satisfies weak testability, for each hardware element of the data path, there exist paths from some primary inputs to the element to justify some values on its output and paths from the hardware element to some primary outputs to propagate some values on its output. For a weakly testable data path, a sequential ATPG tool can generate a test sequence with high fault efficiency in a short test generation time. In this paper, we introduce a notion called test knowledge, use of which by commercial ATPG tools can further decrease the test generation time and increase the fault efficiency in weakly testable data paths. This test knowledge is information which is relevant to structure of weakly testable data paths, and also easy to find. Use of this test knowledge to facilitate the test generation and increase the testability of data path is established in experimental results
Keywords :
automatic test pattern generation; design for testability; integrated circuit testing; logic testing; sequential circuits; RTL description; high fault efficiency; large VLSI circuits; register-transfer level data paths; sequential ATPG tool; test generation; test generation time; test knowledge; weak testability; weakly testable data paths; Automatic test pattern generation; Circuit faults; Circuit testing; Costs; Data mining; Design for testability; Logic testing; Sequential analysis; Sequential circuits; Very large scale integration;
Conference_Titel :
Test Symposium, 1999. (ATS '99) Proceedings. Eighth Asian
Conference_Location :
Shanghai
Print_ISBN :
0-7695-0315-2
DOI :
10.1109/ATS.1999.810722