Low-power design methodology: power estimation and optimization

The author presents a summary of recent results and the state of the art in low-power computer-aided design techniques for integrated circuits. The increasing power consumption levels of integrated circuits (ICs) have become a major concern of the semiconductor industry. Excessive power dissipation causes overheating, which can lead to soft errors or permanent damage. It also limits battery life in portable equipment. Thus, there is a need for a low-power design methodology, which includes computer-aided design (CAD) capabilities for estimating and optimizing (reducing) the power consumption of a proposed design. In this paper, the author discusses the CAD techniques and tools that have been developed for low-power design, specifically for digital CMOS VLSI chips.