On compact test sets for multiple stuck-at faults for large circuits

Author

Kajihara, Seiji ; Murakami, Atsushi ; Kaneko, Tomohisa

Author_Institution

Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Fukuoka, Japan

fYear

1999

fDate

1999

Firstpage

20

Lastpage

24

Abstract

This paper investigates test sets with high fault coverage for multiple stuck-at faults of large combinational circuits and fully scanned sequential circuits. We show the ability of multiple fault detection of test sets generated for single stuck-at-faults, then give a procedure for generating a compact test set with high multiple fault coverage. Results show that our method can generate a test set with complete fault coverage for many circuits, and the size of the test set is smaller than previously reported ones

Keywords

automatic test pattern generation; combinational circuits; fault diagnosis; integrated circuit testing; logic testing; sequential circuits; vectors; compact test sets; fully scanned sequential circuits; high fault coverage; large combinational circuits; large logic circuits; multiple fault detection; multiple stuck-at faults; single stuck-at-faults; vector pair analysis; Circuit faults; Circuit testing; Combinational circuits; Compaction; Delay; Electrical fault detection; Electronic equipment testing; Fault detection; Sequential analysis; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1999. (ATS '99) Proceedings. Eighth Asian

Conference_Location

Shanghai

ISSN

1081-7735

Print_ISBN

0-7695-0315-2

Type

conf

DOI

10.1109/ATS.1999.810724

Filename

810724