Title :
The new test wrapper design for core testing in packet-switched micro-network on chip
Author :
Aghaei, Babak ; Babaei, Shahram
Author_Institution :
Dept. of Eng., Islamic Azad Univ., Malekan, Iran
Abstract :
Recent advances in packet-switched micro-network on chip arise great challenges in test and testability issues. This paper presents a novel test wrapper design for embedded cores in NoC. This wrapper uses functional ports for test data transmission. We assembled proposed test wrapper on a processor during hierarchical simulation. Clearly, simulation results show our proposed wrapper works correctly.
Keywords :
circuit simulation; microprocessor chips; network synthesis; network-on-chip; packet switching; core testing; functional ports; hierarchical simulation; packet-switched micronetwork on chip; processor; test data transmission; test wrapper design; testability; Assembly; Data communication; Design engineering; Electronic equipment testing; Intelligent transportation systems; Network-on-a-chip; Power engineering and energy; Protocols; System testing; System-on-a-chip; IEEE P1500; Network on Chi; Test Wrapper;
Conference_Titel :
Power Electronics and Intelligent Transportation System (PEITS), 2009 2nd International Conference on
Conference_Location :
Shenzhen
Print_ISBN :
978-1-4244-4544-8
DOI :
10.1109/PEITS.2009.5406770
