Logic-compatible embedded DRAM design for memory intensive low power systems

Circuit techniques for enabling a low power logic-compatible embedded DRAM (eDRAM) are presented. A boosted 3T gain cell utilizes preferential storage node boosting to improve data retention time and increase read margin. A regulated bit-line write scheme is equipped with a steady-state storage node voltage monitor to overcome the data `1´ write disturbance problem. An adaptive and die-to-die adjustable read reference bias generator is proposed to cope with PVT variations. Measurement data from 65nm test chips demonstrate a >1.0msec retention time at 0.9V, 85°C and a <;100μW per Mb refresh power at 1.0V, 85°C which translates into a 50% reduction in static power compared to a power gated SRAM.