Title :
Defining SRAM resistive defects and their simulation stimuli
Author :
van de Goor, A.J. ; Simonse, J.E.
Author_Institution :
Fac. of Inf. Technol. & Syst., Delft Univ. of Technol., Netherlands
Abstract :
This paper presents a structured way of deriving new functional fault models, based on the insertion of resistive defects into the electrical schematic of an SRAM. A taxonomy of the set of possible electrical faults is given, a set of primitive patterns to drive the electrical level simulator is derived, the existing notation for functional faults is revisited, and simulation results prove the existence of new functional faults
Keywords :
CMOS memory circuits; SPICE; SRAM chips; circuit simulation; fault simulation; integrated circuit testing; 0.5 mum; CMOS SRAM technology; SPICE simulation; SRAM resistive defect definition; electrical level simulator; functional fault models; functional fault notation; primitive patterns; resistive defect insertion; simulation stimuli; Bismuth; Circuits; Random access memory; Timing;
Conference_Titel :
Test Symposium, 1999. (ATS '99) Proceedings. Eighth Asian
Conference_Location :
Shanghai
Print_ISBN :
0-7695-0315-2
DOI :
10.1109/ATS.1999.810726
