Vector-based functional fault models for delay faults

Author

Pomeranz, Irith ; Reddy, Sudhakar M.

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA

fYear

1999

fDate

1999

Firstpage

41

Lastpage

46

Abstract

Several functional delay fault models have been proposed before to allow functional test generation for delay faults. In this work, we extend these models to accommodate functional descriptions where inputs and outputs are more naturally represented by vectors carrying non-binary values. Such vectors are typical of high-level functional descriptions. Experimental results show that using the vector-based models does not result in loss of gate-level path delay fault coverage

Keywords

automatic test pattern generation; combinational circuits; delay estimation; fault simulation; integrated circuit testing; logic testing; vectors; combinational circuits; delay faults; functional delay fault models; functional test generation; gate-level path delay fault coverage; high-level functional descriptions; large circuits; nonbinary values; vector-based functional fault models; Circuit faults; Circuit testing; Cities and towns; Combinational circuits; Design for testability; Fault detection; Hardware; Logic testing; Propagation delay; Robustness;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1999. (ATS '99) Proceedings. Eighth Asian

Conference_Location

Shanghai

ISSN

1081-7735

Print_ISBN

0-7695-0315-2

Type

conf

DOI

10.1109/ATS.1999.810727

Filename

810727