Linearity enhancement in Digital-to-Analog Converters using a modified decoding architecture

In this paper, a novel architecture for implementation of segmented Digital-to-Analog Converters (DACs) has been proposed. In this architecture, the array of unit elements has been divided into four similar sub-arrays and binary to thermometry conversion is performed in three control levels. The proposed control levels are connected to the sub-arrays in different sequences, thus different analog outputs according to the random mismatch distribution of sub-arrays is achieved. This architecture in addition to an extra multiplexer provides the possibility to test the chip after its fabrication in different sequences and the most linear one based on static linearity metric (INL-Yield) or dynamic performance (SFDR) be selected. Monte-Carlo simulations for an 8-bit unary DAC has shown that in the proposed architecture the probability of achieving a more linear DAC is much more than conventional one. Hence, preserving the required linear output, the mismatch of the unary elements could be increased i.e. the area of the unary array and the whole chip could be decreased.