Title :
Research and implementation of a high speed test generation for ultra large scale combinational circuits
Author :
Zeng, Zhide ; Chen, Jihua ; Cao, Hefeng
Author_Institution :
Dept. of Comput. Sci., Nat. Univ. of Defense Technol., Hunan, China
Abstract :
In this paper a high-speed test generation method for ultra large scale combinational circuits and full-scan circuits is presented. This method adopts the finite backtracking test pattern generation method to generate test pattern, and uses the parallel-pattern single-fault propagating method with n (machine word length) test vectors to validate the fault coverage. The test generation and fault simulation are integrated with n to 1 tightly coupled mode. The method obtains desired results: shorter test pattern length, higher fault coverage and efficiency from execution of 10 ISCAS-85 benchmark circuits
Keywords :
ULSI; automatic test pattern generation; combinational circuits; fault simulation; high-speed integrated circuits; integrated circuit testing; logic testing; ISCAS-85 benchmark circuits; fault coverage; fault simulation; finite backtracking test pattern generation; full-scan circuits; high-speed test generation method; parallel-pattern single-fault propagating method; test pattern generation; test pattern length; test vectors; tightly coupled; ultra large scale combinational circuits; AC generators; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Computer science; Large-scale systems; Life estimation; Read only memory; Test pattern generators;
Conference_Titel :
Test Symposium, 1999. (ATS '99) Proceedings. Eighth Asian
Conference_Location :
Shanghai
Print_ISBN :
0-7695-0315-2
DOI :
10.1109/ATS.1999.810731
