Pattern sensitivity: a property to guide test generation for combinational circuits

We propose a property of input patterns called sensitivity to guide test generation for combinational circuits. Under a sensitive pattern, a change in a single input value causes a change in an output value. Such a pattern is likely to be sensitive to the presence of a fault, and is likely to result in fault detection. We describe a test generation procedure that generates sensitive patterns based on logic simulation of the fault free circuit. The procedure achieves complete fault coverage for the circuits considered