A BIST TPG approach for interconnect testing with the IEEE 1149.1 STD

Author

Feng, W. ; Huang, W.-K. ; Meyer, F.J. ; Lombardi, F.

Author_Institution

Lucent Technol., Allentown, PA, USA

fYear

1999

fDate

1999

Firstpage

95

Lastpage

100

Abstract

In this paper, a novel architecture for built-in self test (BIST) and different designs for both the control and data test pattern generators (CTPG and DTPG) are proposed for interconnect testing using the IEEE standard 1149.1. A general and complete procedure to implement this architecture is also presented. For the DTPG design, the complementary counting sequence (as an example of a maximal independent test set) is used for fault detection. One of the main features of this design is its independence with respect to the type of cell in the chain. A novel design is proposed for the CTPG to avoid damage to the circuit as well as to guarantee 100% fault coverage with low hardware overhead and time complexity

Keywords

IEEE standards; automatic test pattern generation; built-in self test; computational complexity; fault diagnosis; integrated circuit interconnections; integrated circuit testing; BIST; CTPG; DTPG; IEEE standard 1149.1; TPG; complementary counting sequence; control test pattern generators; data test pattern generators; fault coverage; fault detection; hardware overhead; interconnect testing; maximal independent test set; time complexity; Automatic testing; Boolean functions; Built-in self-test; Circuit faults; Circuit testing; Electrical fault detection; Hardware; Integrated circuit interconnections; Sequential analysis; Software testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1999. (ATS '99) Proceedings. Eighth Asian

Conference_Location

Shanghai

ISSN

1081-7735

Print_ISBN

0-7695-0315-2

Type

conf

DOI

10.1109/ATS.1999.810735

Filename

810735