Procedure to overcome the Byzantine General´s problem for bridging faults in CMOS circuits

The resistance of a bridge fault is critical in determining whether the fault can be detected. In order to simulate the effects of a bridging fault it´s necessary to determine the intermediate voltage of the shorted nodes and compared it to the logic threshold voltage of the driven gates. We present an algorithm, which can be used to overcome the Byzantine General´s problem during the fault simulation and test pattern generation. The algorithm applies to very low bridging fault resistance, and modifies it to apply for different values of BF resistance. This algorithm applies to external and internal inter-gate bridging faults. Moreover, the algorithm is much faster than previous ones since no SPICE simulation is required. The accuracy is ±0.01 V compared with SPICE simulation in the interval of intermediate voltage