A novel fault-detection technique for the parallel multipliers and dividers

Author

Arjhan, Chanyutt ; Deshmukh, Raghvendra G.

Author_Institution

Dept. of Electr. & Comput. Sci. & Eng., Florida Inst. of Technol., Melbourne, FL, USA

fYear

1999

fDate

1999

Firstpage

127

Lastpage

132

Abstract

A new fault-detection technique, ω-scan, for a specific interconnection of the parallel Braun-multiplier and the parallel divider is presented. The fault-detection model, Pair Faults (pf), and the concept of Multiple Fault Boundaries (MFBs) are generalized with new supporting lemmas. The new technique´s application is used to detect all multiple stuck-at faults of the carry save adder (CSA) tree and the adder-subtractor (AS) tree with or without being iterative logic arrays (ILAs) and with or without summand-generator embodiment. Fault location is limited. There are 2(n+2) test patterns to be applied to an n×n CSA tree and its associated test gates and 2(n+4) patterns to an m/n AS tree only

Keywords

boundary scan testing; carry logic; design for testability; dividing circuits; fault diagnosis; integrated circuit interconnections; integrated circuit layout; integrated circuit testing; logic arrays; logic testing; multiplying circuits; parallel architectures; ω-scan; adder-subtractor tree; carry save adder tree; fault-detection model; fault-detection technique; functional testing; interconnection layout; iterative logic arrays; multiple fault boundaries; multiple stuck-at faults; pair faults; parallel Braun-multiplier; parallel divider; summand-generator embodiment; test patterns; Argon; Computer science; Controllability; Cost function; Electrical fault detection; Fault detection; Performance gain; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1999. (ATS '99) Proceedings. Eighth Asian

Conference_Location

Shanghai

ISSN

1081-7735

Print_ISBN

0-7695-0315-2

Type

conf

DOI

10.1109/ATS.1999.810740

Filename

810740