A fault partitioning method in parallel test generation for large scale VLSI circuits

Author

Zeng, Zhide ; Chen, Jihua ; Liu, Pengxia

Author_Institution

Dept. of Comput. Sci., Nat. Univ. of Defense Technol., Hunan, China

fYear

1999

fDate

1999

Firstpage

133

Lastpage

137

Abstract

Firstly we propose a theoretical method to increase the speed-up ratio in parallel test generation based on fault partitioning. Based on this method, a new fault partitioning approach-Backward Fault Partitioning based on Output fan-in Cones (BFPOC)-is presented which combines the relevant fault identification and shortest path sensitization. In addition, BFPOC is compared via experiments with the approach of Toward Fault Partitioning based on Input fan-out Cones (TFPIC) proposed by Bannerjee (1994) and the widely used method-Equal Distance Partitioning of Fault Sequence (EDPFS) respectively. The results show that in a large-scale parallel processing environment, BFPOC can obtain higher speed-up ratio than the other two approaches

Keywords

VLSI; automatic test pattern generation; fault diagnosis; fault simulation; integrated circuit testing; logic partitioning; logic testing; parallel processing; backward fault partitioning; fault identification; fault partitioning method; input fan-out cones; large scale VLSI circuits; large-scale parallel processing environment; output fan-in cones; parallel test generation; path sensitization; simultaneous fault simulation; speed-up ratio; Circuit faults; Circuit testing; Computer science; Feedback circuits; Large-scale systems; Parallel processing; Partitioning algorithms; System testing; Very large scale integration; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1999. (ATS '99) Proceedings. Eighth Asian

Conference_Location

Shanghai

ISSN

1081-7735

Print_ISBN

0-7695-0315-2

Type

conf

DOI

10.1109/ATS.1999.810741

Filename

810741