Title :
Fault simulation techniques to reduce IDDQ measurement vectors for sequential circuits
Author :
Higami, Yoshinobu ; Takamatsu, Yuzo ; Saluja, Kewal K. ; Kinoshita, Kozo
Author_Institution :
Ehime Univ., Matsuyama, Japan
Abstract :
This paper presents fault simulation techniques for selecting a small number of IDDQ measurement vectors from a given test sequence while maintaining the original fault coverage. The proposed method covers a class of bridging faults and uses parallel fault simulation wherever possible. Experimental results are presented to demonstrate the effectiveness of the proposed method
Keywords :
CMOS logic circuits; electric current measurement; fault simulation; integrated circuit testing; logic simulation; logic testing; sequential circuits; vectors; CMOS circuits; IDDQ measurement vector reduction; bridging faults; fault coverage; fault simulation techniques; logic simulation; parallel fault simulation; sequential circuits; test sequence; Circuit faults; Circuit simulation; Sequential circuits;
Conference_Titel :
Test Symposium, 1999. (ATS '99) Proceedings. Eighth Asian
Conference_Location :
Shanghai
Print_ISBN :
0-7695-0315-2
DOI :
10.1109/ATS.1999.810742
