Identification of redundant crosspoint faults in sequential PLAs with fault-free hardware reset

Author

Yamada, Teruhiko ; Kotake, Toshinori ; Takahashi, Hiroshi ; Yamazaki, Koji

Author_Institution

Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan

fYear

1999

fDate

1999

Firstpage

269

Lastpage

274

Abstract

We present a technique for identifying redundant crosspoint faults in, sequential PLAs with fault-free hardware reset. This technique can find most redundant crosspoint faults efficiently. Experimental results show that about 7% of crosspoint faults are redundant on an average in the sequential PLAs synthesized by a commercial design tool SYNARIO for MCNC LGSynth89 finite-state machine benchmarks

Keywords

circuit analysis computing; design for testability; fault simulation; integrated circuit testing; logic testing; programmable logic arrays; redundancy; sequential circuits; FSM benchmarks; SYNARIO; fault identification; fault-free hardware reset; finite-state machine benchmarks; redundant crosspoint faults; sequential PLAs; Benchmark testing; Circuit faults; Circuit synthesis; Circuit testing; Decoding; Fault diagnosis; Hardware; Programmable logic arrays; Sequential analysis; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1999. (ATS '99) Proceedings. Eighth Asian

Conference_Location

Shanghai

ISSN

1081-7735

Print_ISBN

0-7695-0315-2

Type

conf

DOI

10.1109/ATS.1999.810762

Filename

810762

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3389564