Title :
A high-level synthesis approach to partial scan design based on acyclic structure
Author :
Takasaki, Tomoya ; Inoue, Tomoo ; Fujiwara, Hideo
Author_Institution :
Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
Abstract :
This paper presents a high-level synthesis method for testable data paths with partial scan design based on acyclic structure. For a given scheduled data flow graph, we propose a heuristic method of operational unit binding and register binding to minimize the number of scan registers for acyclic structure without sacrifice of area overhead
Keywords :
VLSI; data flow graphs; design for testability; high level synthesis; scheduling; sequential circuits; acyclic structure; area overhead; heuristic method; high-level synthesis approach; operational unit binding; partial scan design; register binding; scan registers; scheduled data flow graph; testable data paths; Circuit testing; Costs; Feedback loop; Flip-flops; Flow graphs; High level synthesis; Registers; Sequential analysis; Sequential circuits; Very large scale integration;
Conference_Titel :
Test Symposium, 1999. (ATS '99) Proceedings. Eighth Asian
Conference_Location :
Shanghai
Print_ISBN :
0-7695-0315-2
DOI :
10.1109/ATS.1999.810768
