• DocumentCode
    3389741
  • Title

    A new algorithm for retiming-based partial scan

  • Author

    Huang, Zulan ; Ye, Yizheng ; Mao, Zhigang

  • Author_Institution
    Microelectron. Center, Harbin Inst. of Technol., China
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    327
  • Lastpage
    332
  • Abstract
    In this paper, a new algorithm for retiming-based partial scan is presented. The proposed technique achieves a good-for-test configuration by moving registers to a specific set of edges that is selected for scan. As a part of our work, an algorithm of counting how many cycles that contain a specific edge is given. Moreover, the validity to place some registers on a definite set of edges by retiming is also discussed. Comparing with the existed retiming-based methods, our approach is characterized by less area overhead and comparable fault coverage. Experimental results of some ISCAS´89 benchmarks showed the effectiveness of our method
  • Keywords
    boundary scan testing; circuit analysis computing; flip-flops; graph theory; integrated circuit testing; logic testing; timing; area overhead reduction; fault coverage; good-for-test configuration; retiming-based partial scan; Automatic testing; Circuit faults; Circuit testing; Electronic switching systems; Feedback; Flip-flops; Microelectronics; Registers; Sequential analysis; Sequential circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 1999. (ATS '99) Proceedings. Eighth Asian
  • Conference_Location
    Shanghai
  • ISSN
    1081-7735
  • Print_ISBN
    0-7695-0315-2
  • Type

    conf

  • DOI
    10.1109/ATS.1999.810771
  • Filename
    810771