Peripheral partitioning and tree decomposition for partial scan

We propose a new partial scan technique that incurs significantly less area overhead than the pipeline technique (all feedback cycles including self-loops are broken) and yet achieves very high test coverage in short CPU times. Our proposal selects scan flip-flops so that the circuit satisfies two key properties in the test mode. First, the circuit is partitioned into peripherally interacting finite state machines (peripheral partitions). Peripheral partitions do not have combinational paths between flip-flops belonging to different partitions. Second, the flip-flop dependency graph (S-graph) of each peripheral partition has a tree structure. Our technique does not require self-loops to be broken. We believe that peripheral partitions with tree structure S-graphs inherently require low sequential test generation resources. We develop an efficient algorithm for peripheral partitioning and tree decomposition of the S-graph. The scan flip-flop selection algorithm iteratively partitions the S-graph into disjoint sub-graphs with the tree structure. We report results on all the large circuits in the ISCAS 89 benchmark set. These results show that our technique produces scan circuits for which very high (near 100%) fault efficiency is achievable in extremely short CPU times. The high fault efficiencies achieved by our technique are comparable to that of pipeline circuits. However, the area overhead for our technique is significantly less than the pipeline case