DocumentCode
3389822
Title
Minimizing the number of programming steps for diagnosis of interconnect faults in FPGAs
Author
Yu, Yinlei ; Xu, Jian ; Huang, Wei Kang ; Lombardi, Fabrizio
Author_Institution
ASIC State Key Lab., Fudan Univ., Shanghai, China
fYear
1999
fDate
1999
Firstpage
357
Lastpage
362
Abstract
This paper presents a procedure to diagnose single faults in SRAM based FPGAs. The procedure is nonadaptive and requires six programming steps to give the exact position and type of any single fault in a FPGA. It is proved that the number of programming steps required for the procedure is minimal for a non-adaptive procedure with the given interconnect model
Keywords
PLD programming; fault diagnosis; fault location; field programmable gate arrays; integrated circuit interconnections; integrated circuit testing; logic testing; FPGA testing; SRAM-based FPGAs; interconnect faults diagnosis; interconnect model; nonadaptive procedure; programming steps; single faults; Application specific integrated circuits; Circuit faults; Fault detection; Fault diagnosis; Field programmable gate arrays; Integrated circuit interconnections; Laboratories; Logic programming; Switches; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 1999. (ATS '99) Proceedings. Eighth Asian
Conference_Location
Shanghai
ISSN
1081-7735
Print_ISBN
0-7695-0315-2
Type
conf
DOI
10.1109/ATS.1999.810775
Filename
810775
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